1. Field of the Invention
The present invention relates to a managing system and synchronization method for a plurality of voltage regulator module VRM-type modules.
Specifically, the invention relates to a managing system for managing a plurality of VRMs, which are associated with a plurality of microprocessors and connected in parallel together between first and second voltage references, said VRMs having output terminals connected together and arranged to communicate over a common bus, wherein said managing system comprises at least one error amplifier being input an output voltage signal from said plurality of VRMs, a reference voltage, and a droop voltage produced through an equivalent droop resistor receiving an output current signal from said plurality of VRMs and being connected to said common bus, said error amplifier effecting a comparison of said input signals to generate a control voltage signal to said plurality of VRMs.
The invention further relates to a method of synchronizing a plurality of VRMs associated with a plurality of microprocessors and connected in parallel together between first and second voltage references, said VRMs having output terminals connected to a common bus line, and relates to a synchronization circuit implementing the method.
2. Description of the Related Art
As is well known, supply sharing architectures offer a number of advantages in microprocessor-based systems. Such systems must be equipped with load current regulators, e.g., of the so-called point-of-load type, to provide high levels of accuracy as well as the dynamic load needed by the microprocessors.
However, VRMs (Voltage Regulator Modules) are used in place of the point-of-load regulators in up-to-date microprocessor architectures. VRMs afford effective voltage handling, and come with standard form factors to tailored specifications for different end user's requirements.
In particular, multiprocessor systems for such computers as Servers and Workstations employ a plurality of microprocessors to meet the requirements of these substrata. For internal voltage handling, the systems include one VRM for each microprocessor. In this way, the whole system is ensured adequate modularity and scale economy.
Multi-processor systems conventionally comprise a plurality of microprocessors, all connected to the same supply voltage and ground references, VDD and GND, respectively. It is sound practice to have all the microprocessors powered over a common supply-to-ground path, for improved speed and integrity of the interconnect signals between them.
In addition, VRMs usually have output terminals on a common plane. Thus, a managing method is demanded to equalize the load among them, especially to apportion them the load current equally for proper operation of the parallel connection.
It should be considered, in this respect, that processing units (CPU) comprising such microprocessors draw different current levels according to their working conditions. Thus, by controlling the current distribution through equalized VRM load levels, a higher degree of reliability from reduced terminating peaks of the individual VRMs and improved response to load transients can be achieved.
For such multi-processor systems to operate properly, it should be possible to have the VRMs inter-related operatively under all working conditions, such as at initial turn-on (start-up, soft-start), operation of module-protecting mechanisms (e.g., in overload OCP or overvoltage OVP situations), and re-initializing and short-circuiting of the cascaded module output plane (HICCUP).
Known are two different basic techniques for paralleling a plurality of VRMs, namely the master-slave and the average current sharing methods.
In particular, a conventional current managing system for VRMs as above, using a current sharing technique, is described in an article “Current Sharing Technique for VRMs” by M. Walters, Intersil Corp., May 2000, and shown schematically in FIG. 1.
According to that article, each VRM 1 includes a managing system 2, itself including an error amplifier 3.
The error amplifier 3 is input an output voltage signal Vout from the VRM 1 and a reference voltage Vref, and will compare them to generate a control voltage signal control to VRM 1.
In particular, the error amplifier 3 has its input connected to a first summing node X1 that receives the reference voltage Vref as a positive addend, and receives a droop voltage Vdroop, a control voltage Vshare, and a total voltage Vtot resulting from the summation, performed in a second summing node X2, of the output voltage signal Vout from the VRM 1, and a supply voltage reference such as a ground voltage GND.
The managing system 2 includes an equivalent droop resistor Rdroop receiving an output current signal Iout from the VRM 1 and being connected to supply the droop voltage Vdroop to the first summing node X1.
In addition, the output current signal Iout from the VRM 1 is passed into a first control resistor Rshare1 arranged to supply a first local control or share voltage Vls1 to a third summing node X3, which is connected to a controller 4 adapted to supply the control voltage Vshare to the first summing node X1.
The third summing node X3 is input, as a negative addend, a second local control voltage Vls2 from a second control resistor Rshare2 connected, in series with said first control resistor Rshare1, to a current sharing bus 5.
Let us see now how the conventional managing system 2 shown in FIG. 1 operates.
The information in the output current Iout from the VRM 1 is used to shift the reference for the control loop proportionally to the load (the so-called voltage positioning) through the equivalent droop resistor Rdroop. Also, the output current Iout is converted into voltages Vls1, Vls2 by means of the control resistors Rshare 1, Rshare2, and is used in the current sharing loop of the managing system 2 that includes the controller 4 and the error amplifier 3.
Within each module 1, the first local control voltage Vls1 is taken to the common bus 5 through the second control resistor Rshare2. Thus, the voltage on this bus is made proportional to the average current of all modules 1, and the voltage difference Vls2 across the second control resistor Rshare2 proportional to the difference between the current of the individual modules 1 and said average current.
This information about the individual modules 1 with respect to the mean of all modules is passed to the controller 4, and through the first summing node X1, onward to the error amplifier 3, whose output error signal is used, following appropriate amplification and filtering in a conventional manner, to shift the feedback of the error amplifier 3 and generate the control voltage signal Vcontrol.
Therefore, the regulated output voltage signal Vout from each module 1 will be:Vout=Vref−Vdroop−Vshare.
It should be further noted that the droop voltage Vdroop is proportional to the output current signal Iout, and the control voltage Vshare is proportional to the ratio Iload/N-Iout, where N is the number of VRMs 1 in parallel within the microprocessor system, and Iload is the load current.
In conclusion, the control voltage V share allows unbalance among the various VRMs 1 to be adjusted in order that their output currents are equalized.
While advantageous on several counts, this prior solution has a number of drawbacks. Specifically, the sums of the internal VRM signals must be performed by voltage and require the availability of amplifiers, which deteriorates the dynamic response and precision of the VRMs 1 as well as of the microprocessor system as a whole.
Using additional resistors to perform the sums in a passive manner would lower the individual contributions, so that pre-amplification becomes necessary and the construction of the managing system 2 becomes more complicated.
Multi-processor systems having a plurality of VRMs also pose the problem of how to synchronize the individual VRMs in parallel, which problem grows in importance with the number of modules.